View TMP93CM40_4110233.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L Series
TMP93CM40
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions.
**CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts (NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2, RUN is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
TMP93CM40
Low Voltage/Low Power
CMOS 16-Bit Microcontroller
TMP93CM40F 1. Outline and Device Characteristics
The TMP93CM40 is high-speed, advanced 16-bit microcontroller developed for controlling medium to large-scale equipment. They enable low voltage and low-power-consumption operation. The TMP93CM40 is housed in 100-pin flat packages. The device characteristics are as follows: (1) Original 16-bit CPU (900/L CPU) TLCS-90 instruction mnemonic upward compatible 16-Mbyte linear address space General-purpose registers, register bank system 16-bit multiplication, 16-bit division, bit transfer and bit manipulation instructions Micro DMA: 4 channels (1.6 s per 2 bytes at 20 MHz) (2) Minimum instruction execution time: 200 ns at 20 MHz (3) Internal RAM: 2 Kbytes Internal ROM: 32 Kbytes (4) External memory expansion Can be expanded up to 16 Mbytes (for both programs and data). AM8/ AM16 pin (select the external data bus width) Can mix 8- and 16-bit external data buses. (Dynamic bus sizing) (5) 8-bit timer: (6) 8-bit PWM timer: (7) 16-bit timer: 2 channels 2 channels 2 channels
(8) 4-bit pattern generator: 2 channels (9) Serial interface: (10) 10-bit AD converter: 2 channels 8 channels
030619EBP1
The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions.
93CM40-1
2004-02-10
TMP93CM40
(11) Watchdog timer (12) Chip select and wait controller: 3 blocks (13) Interrupt functions: 29 9 CPU interrupts (SWI instruction, and illegal instruction) 14 internal interrupts 6 external interrupts (14) I/O ports: 79 (15) Standby function: 4 HALT modes (RUN, IDLE2, IDLE1, STOP) (16) Clock gear function Dual clock operation Clock gear: High-frequency clock can be changed from fc to fc/16. (17) Wide range of operating voltage Vcc = 2.7 to 5.5 V (18) Package Type No.
TMP93CM40F
7-level priority can be set.
Package
P-QFP100-1414-0.50
93CM40-2
2004-02-10
TMP93CM40
PA0 to PA6 PA7 (SCOUT) P50 to P57 (AN0 to AN7) AVCC AVSS VREFH VREFL (TXD0) P90 (RXD0) P91 (SCLK0/ CTS0 ) P92 (TXD1) P93 (RXD1) P94 (SCLK1) P95 (PG 00) P60 (PG 01) P61 (PG 02) P62 (PG 03) P63 (PG 10) P64 (PG 11) P65 (PG 12) P66 (PG 13) P67 (TI0) P70
Port A 900/L CPU 10-bit 8-channel AD Converter XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits F SR PC Interrupt controller Pattern generator (channel 0) Pattern generator (channel 1) Highfrequency OSC Lowfrequency OSC
VCC [3] VSS [3] X1 X2 CLK XT1 XT2 AM8/ AM16
EA RESET
Serial I/O (channel 0) Serial I/O (channel 1)
ALE TEST1 TEST2 P87 (INT0)
NMI
Watchdog timer
WDTOUT
2-Kbyte RAM
Port 0
P00 to P07 (AD0 to AD7) P10 to P17 (AD8 to AD15/A8 to A15) P20 to P27 (A0 to A7/A16 to A23) P30 ( RD ) P31 ( WR ) P32 ( HWR )
8-bit timer (Timer 0) 8-bit timer (Timer 1)
Port 1
(TO1) P71
Port 2
(TO2) P72
8-bit PWM (Timer 2) 8-bit PWM (Timer 3) 32-Kbyte ROM
(TO3) P73
Port 3
P33 ( WAIT ) P34 ( BUSRQ ) P35 ( BUSAK ) P36 ( R / W ) P37 ( RAS )
(INT4/TI4) P80 (INT5/TI5) P81 (TO4) P82 (TO5) P83 (INT6/TI6) P84 (INT7/TI7) P85 (TO6) P86
16-bit timer (Timer 4) 16-bit timer (Timer 5) CS/WAIT controller (3 block)
P40 ( CS0 / CAS0 ) P41 ( CS1 / CAS1 ) P42 ( CS2 / CAS2 )
Figure 1.1 TMP93CM40 Block Diagram
93CM40-3
2004-02-10
TMP93CM40
2.
Pin Assignment and Functions
The assignment of input and output pins for the TMP93CM40, their names and functions are described below.
2.1
Pin Assignment
Figure 2.1.1 shows pin assignment of the TMP93CM40F.
Programmable Pull Pull down up Stepping motor control
Programmable Pull Pull up down
TMP93CM40 P66/PG12 P67/PG13 VSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC
NMI
Pin No. 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
Pin No.
TMP93CM40
88 P65/PG11 87 P64/PG10 86 P63/PG03 85 P62/PG02 84 P61/PG01 83 P60/PG00 82 P42/ CS2 / CAS2 81 P41/ CS1 / CAS1 80 P40/ CS0 / CAS0 79 P37/ RAS 78 P36/ R / W 77 P35/ BUSAK 76 P34/ BUSRQ 75 P33/ WAIT 74 P32/ HWR 73 P31/ WR 72 P30/ RD 71 70 69 68 67 66 65 64 63 P27/A7/A23 P26/A6/A22 P25/A5/A21 P24/A4/A20 P23/A3/A19 P22/A2/A18 P21/A1/A17 P20/A0/A16 VCC
ADC
Timer
P70/TI0 P71/TO1 P72/TO2 P73/TO3 P80/INT4/TI4 P81/INT5/TI5 P82/TO4 P83/TO5 P84/INT6/TI6 P85/INT7/TI7 P86/TO6 P87/INT0 P90/TXD0 P91/RXD0 P93/TXD1 P94/RXD1 P95/SCLK1 AM8/ AM16 CLK VCC VSS
Top view QFP100
62 VSS 61 WDTOUT 60 59 58 57 56 55 54 P17/AD15/A15 P16/AD14/A14 P15/AD13/A13 P14/AD12/A12 P13/AD11/A11 P12/AD10/A10 P11/AD9/A9
SIO
P92/ CTS0 /SCLK0 19
53 P10/AD8/A8 52 P07/AD7 51 P06/AD6 50 P05/AD5 49 P04/AD4 48 P03/AD3 47 P02/AD2 46 P01/AD1 45 P00/AD0 44 VCC 43 ALE 42 PA7/SCOUT 41 PA6 40 PA5 39 PA4 38 PA3
Clock, Mode
X1 X2
EA RESET
P96/XT1 P97/XT2 TEST1 TEST2 PA0 PA1 PA2
Figure 2.1.1 Pin Assignment (100-pin QFP)
93CM40-4
2004-02-10
Memory interface
TMP93CM40
2.2
Pin Names and Functions
The names of the input/output pins and their functions are described below. Table 2.2.1 to Table 2.2.4 show pin names and functions. Table 2.2.1 Pin Names and Functions (1/4)
Pin Names
P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30
RD
Number of Pins
8 8
I/O
I/O 3-state I/O 3-state Output I/O Output Output
Functions
Port 0: I/O port that allows I/O to be selected at the bit level. Address and data (lower): Bits 0 to 7 for address and data bus. Port 1: I/O port that allows I/O to be selected at the bit level. Address and data (upper): Bits 8 to 15 for address and data bus. Address: Bits 8 to 15 for address bus. Port 2: I/O port that allows to be selected at the bit level (with pull-down resistor). Address: Bits 0 to 7 for address bus. Address: Bits 16 to 23 for address bus. Port 30: Output port. Read: Strobe signal for reading external memory. Port 31: Output port. Write: Strobe signal for writing data on pins AD0 to AD7. Port 32: I/O port (with pull-up resistor). High write: Strobe signal for writing data on pins AD8 to AD15. Port 33: I/O port (with pull-up resistor). Wait: Pin used to request CPU bus wait. Port 34: I/O port (with pull-up resistor). Bus request: Signal used to request bus release. Port 35: I/O port (with pull-up resistor). Bus acknowledge: Signal used to acknowledge bus release. Port 36: I/O port (with pull-up resistor). Read/write: 1 represents read or dummy cycle; 0 represents write cycle. Port 37: I/O port (with pull-up resistor). Row address strobe: Outputs RAS strobe for DRAM. Port 40: I/O port (with pull-up resistor). Chip select 0: Outputs 0 when address is within specified address area. Column address strobe 0: Outputs CAS strobe for DRAM when address is within specified address area.
8
1 1 1 1 1 1 1 1 1
Output Output Output Output I/O Output I/O Input I/O Input I/O Output I/O Output I/O Output I/O Output Output
P31
WR
P32
HWR
P33
WAIT
P34
BUSRQ
P35
BUSAK
P36 R/ W P37
RAS
P40
CS0
CAS0
Note:
This device's built-in memory or built-in I/O cannot be accessed by an external DMA controller, using the BUSRQ and BUSAK signals.
93CM40-5
2004-02-10
TMP93CM40
Table 2.2.2 Pin Names and Functions (2/4) Pin Names
P41
CS1 CAS1
Number of Pins
1
I/O
I/O Output Output I/O Output Output Input Input Input Input I/O Output
Functions
Port 41: I/O port (with pull-up resistor). Chip select 1: Outputs 0 if address is within specified address area. Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area. Port 42: I/O port (with pull-down resistor). Chip select 2: Outputs 0 if address is within specified address area. Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area. Port 5: Pin used to input port. Analog input: Pin used to input to AD converter. Pin for reference voltage input to AD converter. (H) Pin for reference voltage input to AD converter. (L) Port 60 to 63: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor). Pattern generator ports: 00 to 03. Port 64 to 67: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor). Pattern generator ports: 10 to 13. Port 70: I/O port (with pull-up resistor). Timer input 0: Timer 0 input. Port 71: I/O port (with pull-up resistor). Timer output 1: Timer 0 or 1 output. Port 72: I/O port (with pull-up resistor). PWM output 2: 8-bit PWM timer 2 output. Port 73: I/O port (with pull-up resistor). PWM output 3: 8-bit PWM timer 3 output. Port 80: I/O port (with pull-up resistor). Timer input 4: Timer 4 count/capture trigger signal input. Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge. Port 81: I/O port (with pull-up resistor). Timer input 5: Timer 4 count/capture trigger signal input. Interrupt request pin 5: Interrupt request pin with rising edge. Port 82: I/O port (with pull-up resistor). Timer output 4: Timer 4 output pin. Port 83: I/O port (with pull-up resistor). Timer output 5: Timer 4 output pin.
P42
CS2 CAS2
1
P50 to P57 AN0 to AN7 VREFH VREFL P60 to P63 PG00 to PG03 P64 to P67 PG10 to PG13 P70 TI0 P71 TO1 P72 TO2 P73 TO3 P80 TI4 INT4 P81 TI5 INT5 P82 TO4 P83 TO5
8 1 1 4
4
I/O Output
1 1 1 1 1
I/O Input I/O Output I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Output
1
1 1
93CM40-6
2004-02-10
TMP93CM40
Table 2.2.3 Pin Names and Functions (3/4) Pin Names
P84 TI6 INT6 P85 TI7 INT7 P86 TO6 P87 INT0 P90 TXD0 P91 RXD0 P92
CTS0
Number of Pins
1
I/O
I/O Input Input I/O Input Input I/O Output I/O Input I/O Output I/O Input I/O Input I/O I/O Output I/O Input I/O I/O I/O I/O Output Output Input Output
Functions
Port 84: I/O port (with pull-up resistor). Timer input 6: Timer 5 count/capture trigger signal input. Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge. Port 85: I/O port (with pull-up resistor). Timer input 7: Timer 5 count/capture trigger signal input. Interrupt request pin 7: Interrupt request pin with rising edge. Port 86: I/O port (with pull-up resistor). Timer output 6: Timer 5 output pin. Port 87: I/O port (with pull-up resistor). Interrupt request pin 0: Interrupt request pin with programmable level/rising edge. Port 90: I/O port (with pull-up resistor). Serial send data 0. Port 91: I/O port (with pull-up resistor). Serial receive data 0. Port 92: I/O port (with pull-up resistor). Serial data send enable 0. (Clear to send) Serial Clock I/O 0. Port 93: I/O port (with pull-up resistor). Serial send data 1. Port 94: I/O port (with pull-up resistor). Serial receive data 1. Port 95: I/O port (with pull-up resistor). Serial clock I/O 1. Port A0 to A6: I/O port. Port A7: I/O port. System clock output: outputs fFPH or fSYS clock. Watchdog timer output pin. Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge or both edges. Clock output: Outputs [fSYS 2] clock. Pulled-up during reset. Can be disabled for reducing noise. External access: The VCC pin should be connected.
1
1 1
1 1 1
SCLK0 P93 TXD1 P94 RXD1 P95 SCLK1 PA0 to PA6 PA7 SCOUT
WDTOUT NMI
1 1 1 7 1 1 1 1
CLK
EA
1
Input
93CM40-7
2004-02-10
TMP93CM40
Table 2.2.4 Pin Names and Functions (4/4) Pin Names
AM8/ AM16
Number of Pins
1
I/O
Input
Functions
Address mode: Selects external data bus width. The VCC pin should be connected. The data bus width for external access is set by the chip select/wait control register, port 1 control register. Address latch enable. Can be disabled for reducing noise. Reset: Initializes TMP93CM40. (with pull-up resistor) High frequency oscillator connecting pin. Port 96: I/O port. (Open-drain output) Low frequency oscillator connecting pin. Port 97: I/O port. (Open-drain output) Low-frequency oscillator connecting pin. TEST1 should be connected with TEST2 pin. Do not connect to any other pins. Power supply pin. (All VCC pins should be connected with the power supply pin.) GND pin (0 V). (All VSS pins should be connected with GND (0 V).) Power supply pin for AD converter. GND pin for AD converter (0 V).
ALE
RESET
1 1 2 1 1 2 3 3 1 1
Output Input Input/Output I/O Input I/O Output Output /Input
X1/X2 P96 XT1 P97 XT2 TEST1/TEST2 VCC VSS AVCC AVSS
Note:
All pins that have built-in pull-up/pull-down resistors (other than the RESET pin) can be disconnected from the built-in pull-up/pull-down resistor by software.
93CM40-8
2004-02-10
TMP93CM40
3.
3.1
Operation
This section describes the functions and basic operation of all blocks of the TMP93CM40 devices.
CPU
The TMP93CM40 has a built-in high performance 16-bit CPU (900/L CPU). (For a description of this CPU's operation, see the sub section TLCS-900/L CPU in the previous section.
3.2
Memory Map
Figure 3.2.1 is a memory map of the TMP93CM40.
000000H 000080H 000100H 000880H
Internal I/O (128 Bytes)
256-byte direct area (n)
Internal RAM (2 KBytes)
External memory
64-Kbyte area (nn)
008000H 008100H
Interrupt vector table area (64 entries 4 bytes)
32-Kbyte internal ROM 010000H
External memory
16-Mbyte area (R) ( R) (R ) (R R8/16) (R d8/16) (nnn)
FFFF00H FFFFFFH
Reserved (256 bytes) ( Internal area)
Note: The 256-byte area from FFFF00H to FFFFFFH cannot be used. Figure 3.2.1 Memory Map
93CM40-9
2004-02-10
TMP93CM40
4.
4.1
Electrical Characteristics
Maximum Ratings (TMP93CM40F)
Parameter
Power supply voltage Input voltage Output current (total) Output current (total) Power dissipation (Ta Storage temperature Operating temperature 85C) Soldering temperature (10 s)
"X" used in an expression shows a frequency for the clock fFPH selected by SYSCR1. The value of "X" changes according to whether a clock gear or a low speed oscillator is selected. An example value is calculated for fc, with gear 1/fc (SYSCR1 "0000")
Symbol
VCC VIN IOL IOH PD TSOLDER TSTG TOPR
Rating
0.5 to 6.5 0.5 to VCC 120 80 600 260 65 to 150 40 to 85 0.5
Unit
V V mA mA mW C C C
Note: The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded.
93CM40-10
2004-02-10
TMP93CM40
4.2
DC Characteristics (1/2)
Parameter Symbol
fc fs
Condition
4 to 16 MHz 30 to 34 kHz (Ta 40 to 85C) 4 to 20 MHz 30 to 34 kHz (Ta 20 to 70C) 4 to 10 MHz 30 to 34 kHz (Ta 40 to 85C) 4.5 V 4.5 V
Min
Typ. (Note 1)
Max
Unit
Power supply voltage AVCC VCC AVSS VSS 0 V
VCC
fc fs fc fs
4.5 5.5 V
2.7 (Note 2) 0.8 0.6 0.3 0.3 VCC 0.25 VCC 0.3 0.2 VCC
Input low voltage
AD0 to AD15 Port 2 to port A (except P87)
RESET , NMI , INT0
VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 VOL VOH1
VCC VCC
VCC
2.7 to 5.5 V
EA , AM8/ AM16
X1, Port 5 Input high voltage AD0 to AD15 Port 2 to port A (except P87)
RESET , NMI , INT0 EA , AM8/ AM16
VCC VCC
4.5 V 4.5 V
2.2 2.0 0.7 VCC VCC 0.3
V
VCC
2.7 to 5.5 V
0.75 VCC VCC 0.3 0.8 VCC
X1 Output low voltage
IOL IOH IOH
1.6 mA (VCC 2.7 to 5.5 V) 400 A (VCC 3 V 400 A (VCC 5 V 10%) 10%) 2.4 4.2
0.45 V
Output high voltage VOH2
Note 1: Typical values are for Ta
25C and VCC
5 V unless otherwise noted. 10%.
Note 2: The operation of the AD converter is guaranteed at 5 V
93CM40-11
2004-02-10
TMP93CM40
4.2
DC Characteristics (2/2)
Parameter Symbol Condition
VEXT 1.5 V REXT 1.1 k (only when VCC 5 V 10%) 0.0 0.2 VIL2 VIL2 VCC VCC fc VIN VIN VCC VCC 0.2 2.0 50 80
Min
Typ. (Note 1)
Max
Unit
Darlington drive current (8 output pins max) Input leakage current Output leakage current Power down voltage (at STOP, RAM back-up)
RESET pull-up resistor
IDAR (Note 2) ILI ILO VSTOP RRST CIO VTH RKL RKH ICC
1.0
3.5
mA
0.02 0.05
5 10 6.0 150 200 10
A V k pF V
0.2 VCC, 0.8 VCC 5V 3V 10% 10%
Pin capacitance Schmitt width RESET , NMI , INT0 Programmable pull-down resistor Programmable pull-up resistor NORMAL (Note 3) NORMAL2 (Note 4) RUN IDLE2 IDLE1 NORMAL (Note 3) NORMAL2 (Note 4) RUN IDLE2 IDLE1 SLOW (Note 3) RUN IDLE2 IDLE1 STOP
1 MHz 0.4 1.0
VCC VCC VCC VCC
5V 3V 5V 3V
10% 10% 10% 10%
10 30 50 100 19 24 17 10 3.5
80 150 150 300 25 30 25 15 5 8 11 7 4 1.2 35 30 20 15 10 A A mA mA k
VCC 5 V 10% fc 20 MHz
VCC 3 V 10% fc 10 MHz (Typ: VCC 3.0 V)
5.5 8.5 4.0 2.5 0.7
VCC 3 V 10% fs 32.768 kHz (Typ: VCC 3.0 V) VCC 2.7 to 5.5 V
20 16 10 5 0.2
Note 1: Typical values are for Ta
25C and VCC
5 V unless otherwise noted.
Note 2: IDAR is guaranteed for up to eight ports. Note 3: ICC measurement conditions (NORMAL, SLOW): Only CPU is operational; output pins are open and input pins are fixed. Note 4: ICC measurement conditions (NORMAL 2): All functions are operational; output pins are open and input pins are fixed.
93CM40-12
2004-02-10
TMP93CM40
4.3
AC Electrical Characteristics
(1) VCC 5V 10%
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Parameter
Osc. period ( x) CLK pulse width A0 to A23 fall CLK valid ALE fall ALE fall A0 to A15 valid CLK hold ALE fall A0 to A 23 hold A0 to A15 hold
RD / WR fall
Symbol
tOSC tCLK tAK tKA tAL tLA tLL tLC tCL tALC tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD
(1 N) WAIT mode (1 N) WAIT mode (1 N) WAIT mode
Variable Min
50 2x 0.5x 1.5x 0.5x 0.5x x 0.5x 0.5x x 1.5x 0.5x 40 20 70 15 20 40 25 20 25 50 25 3.0x 3.5x 2.0x 2.0x 0 x 2.0x 2.0x 0.5x 15 40 55 15 3.5x 3.0x 2.0x 2.5x 1.0x 0.5x 0.5x 2.0x 2.0x 1.0x 0.5x 1.0x 1.5x 0 2.5x 50 200 40 15 2.5x 15 40 40 40 25 40 1.5x 30 65 70 120 90 80 40 55 65 60
16 MHz Min
62.5 85 11 24 16 11 23 6 11 38 44 6 133 154 65 85 0 48 85 70 16 129 108 125 36 206 200 23 16 86 16 85 85 23 6 23 29 64
20 MHz Min
50 60 5 5 10 5 10 0 5 25 25 0 95 110 40 60 0 35 60 45 10 85 70 100 5 175 200 10 10 55 10 60 60 10 0 10 10 40
Max
31250
Max
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ALE high pulse width
RD / WR rise ALE rise A0 to A15 valid RD / WR fall A0 to A23 valid RD / WR fall RD / WR rise A0 to A23 hold A0 to A15 valid D0 to D15 input
A0 to A23 valid
RD fall
D0 to D15 input
D0 to D15 input D0 to D15 hold A0 to A15 output
WR rise
RD low pulse width RD rise RD rise
WR low pulse width
D0 to D15 valid
WR rise
D0 to D15 hold
WAIT input WAIT input WAIT hold
A0 to A23 valid A0 to A15 valid
RD / WR fall
tAWH tAWL tCW tAPH tAPH2 tCP tASRH tASRL tRAC tRAH tRAS tRP tRSH tRSC tRCD tCAC tCAS
A0 to A23 valid A0 to A23 valid
WR rise
Port input
Port hold Port valid
RAS fall
A0 to A23 valid
RAS fall A0 to A15 valid RAS fall D0 to D15 input RAS fall
A0 to A15 hold
RAS low pulse width RAS high pulse width CAS fall RAS rise RAS fall CAS fall RAS rise CAS rise CAS fall
D0 to D15 input CAS low pulse width
AC measuring condition Output level: High 2.2 V/Low 0.8 V, CL 50 pF (However, CL 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , R/ W , CLK, RAS , CAS0 to CAS2 ) Input level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 VCC /Low 0.2 VCC (except AD0 to AD15)
93CM40-13
2004-02-10
TMP93CM40
(2) VCC No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
3V
10%
(TMP93CM40F is guaranteed up to 10 MHz operation.) Symbol
tOSC tCLK
Parameter
Osc. period ( x) CLK pulse width A0 to A23 fall CLK valid ALE fall ALE fall A0 to A15 valid CLK hold ALE fall A0 to A 23 hold A0 to A15 hold
RD / WR fall
Variable Min
100 2x 0.5x 1.5x 0.5x 0.5x x 0.5x 0.5x x 1.5x 0.5x 40 30 80 35 35 60 35 40 50 50 40 3.0x 3.5x 2.0x 2.0x 0 x 2.0x 2.0x 0.5x 25 40 120 40 3.5x 3.0x 2.0x 2.5x 1.0x 0.5x 0.5x 2.0x 2.0x 1.0x 0.5x 1.0x 1.5x 0 2.5x 50 200 60 40 2.5x 25 40 40 55 25 40 1.5x 40 120 110 90 25 160 160 45 25 60 40 10 245 300 130 100 200 40 110 125 115 160 0 75 160 80 10
10 MHz Min
100 160 20 70 15 15 40 15 10 50 100 10 190 225 85
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Max
31250
Max
tAK tKA tAL tLA tLL tLC tCL tALC tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD
(1 N) WAIT mode
ALE high pulse width
RD / WR rise ALE rise A0 to A15 valid RD / WR fall A0 to A23 valid RD / WR fall RD / WR rise A0 to A23 hold A0 to A15 valid D0 to D15 input
A0 to A23 valid
RD fall
D0 to D15 input
D0 to D15 input D0 to D15 hold A0 to A15 output
WR rise
RD low pulse width RD rise RD rise
WR low pulse width
D0 to D15 valid
WR rise
D0 to D15 hold
WAIT input WAIT input WAIT hold
(1 N) WAIT mode (1 N) WAIT mode
A0 to A23 valid A0 to A15 valid
RD / WR fall
tAWH tAWL tCW tAPH tAPH2 tCP tASRH tASRL tRAC tRAH tRAS tRP tRSH tRSC tRCD tCAC tCAS
220 200
ns ns ns
A0 to A23 valid
Port input
5 200
ns ns ns ns ns
A0 to A23 valid Port hold WR rise Port valid A0 to A23 valid
RAS fall RAS fall A0 to A15 valid RAS fall D0 to D15 input RAS fall
160
ns ns ns ns ns ns ns
A0 to A15 hold
RAS low pulse width RAS high pulse width CAS fall RAS rise RAS fall CAS fall RAS rise CAS rise CAS fall
D0 to D15 input
30
ns ns
CAS low pulse width
AC measuring condition Output level: High 0.7 Input level: High 0.9 VCC/Low 0.3 VCC/Low 0.1 VCC, CL VCC 50 pF
93CM40-14
2004-02-10
TMP93CM40
(1) Read cycle
tOSC X1 tCLK CLK tAK A0 to A23 tKA
CS0 to CS2
R/ W
tAWH tAWL
tCW
WAIT
tAPH tAPH2 Port input (Note) tASRH tRSH
RAS
tRP
tRAS tASRL tRAH
CAS0 to CAS2
tRAC tCAS tCAC
tRSC
tRCD tADH
tCA tRR tRAE tHR D0 to D15 tCL
RD
tACH tACL tLC
tRD tADL
AD0 to AD15 tAL ALE tLL
A0 to A15 tLA
Note:
Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative.
93CM40-15
2004-02-10
TMP93CM40
(2) Write cycle
X1
CLK
A0 to A23
CS0 to CS2
R/ W
WAIT
Port output (Note) tCP
RAS
CAS0 to CAS2
WR , HWR
tWW tDW tWD D0 to D15
AD0 to AD15
A0 to A15
ALE
Note:
Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative.
93CM40-16
2004-02-10
TMP93CM40
4.4
AD Conversion Characteristics
AVCC VCC, AVSS VSS
Parameter
Analog reference voltage ( ) Analog reference voltage ( ) Analog input voltage range Analog current for analog reference voltage VCC 5 V 10% 1 VCC 5V 10% 0
10
Symbol
VREFH VREFL VAIN IREF (VREFL - 0 V)
Min
VCC 0.2 V VSS VREFL
Typ.
VCC VSS
Max
VCC VSS 0.2 V
Unit
V
VREFH 0.5 0.02 3.0 1.5 5.0 6 mA A LSB
Error (not including quantizing errors)
Note 1: 1LSB
(VREFH
VREFL) /2
[V] 4 MHz. 10%.
Note 2: The operation above is guaranteed for fFPH
Note 3: The value ICC includes the current which flows through the AVCC pin. Note 4: The operation of this AD converter is guaranteed at 5 V
93CM40-17
2004-02-10
TMP93CM40
4.5
Serial Channel Timing
(1) I/O interface mode a. SCLK input mode
Parameter Variable
Symbol
32.768 kHz (Note 1) Max Min
488 s 91.5 s 152 s 0
10 MHz Min
1600 250 400 0
20 MHz Min
800 100 150 0
Unit
Min
SCLK cycle Output data Rising edge or falling edge (Note 2) of SCLK tSCY tOSS tOHS tHSR tSRD 16x tSCY/2 5x 0 tSCY 5x 100 50
Max
Max
Max
ns ns ns ns 450 ns
SCLK rising edge or falling edge (Note 2) Output data hold SCLK rising edge or falling edge (Note 2) Input data hold SCLK rising edge or falling edge (Note 2) Effective data input
5x
100
336 s
1000
Note 1: System clock is fs, or input clock to prescaler is divisor clock of fs. Note 2: The rising edge is used in SCLK rising mode. The falling edge is used SCLK falling mode. b. SCLK output mode
Parameter Variable
Symbol
32.768 kHz (Note) Max
8192X
10 MHz Min
1.6 1250 120 0
20 MHz Min
0.8 550 20 0
Unit
Min
SCLK cycle (Programmable) Output data SCLK rising edge Output data hold Input data hold Effective data input tSCY tOSS tOHS tHSR tSRD 16X tSCY 5X 150 2x 0 80
Min
488 427 s 60 s 0
Max
250 ms
Max
819.2
Max
409.6 s ns ns ns 550 ns
SCLK rising edge SCLK rising edge SCLK rising edge
tSCY 2x 150
428 s
1250
tSCY SCLK
SCLK output mode (Only rising edge is used) or SCLK input mode (SCLK rising edge mode)
SCLK
SCLK input mode (SCLK falling edge mode)
tOSS 0
tOHS 1 tSRD tHSR 1 Valid 2 Valid 3 Valid 2 3
Output data TxD
Input data RxD
0 Valid
Note: System clock is fs, or input clock to prescaler is divisor clock of fs.
93CM40-18
2004-02-10
TMP93CM40
4.6
Timer/Counter Input Clock (TI0, TI4, TI5, TI6 and TI7)
Parameter Variable
Symbol tVCK tVCKL tVCKH
10 MHz Max Min
900 440 440
20 MHz Min
500 240 240
Min
8X 4X 4X 100 40 40
Max
Max
Unit
ns ns ns
Clock cycle Low level clock pulse width High level clock pulse width
4.7
Interrupt and Capture
(1) NMI , INT0 interrupts Parameter Variable
Symbol tINTAL tINTAH
10 MHz Max Min
400 400
20 MHz Min
200 200
Min
4X 4X
Max
Max
Unit
ns ns
NMI , INT0 low level pulse width NMI , INT0 high level pulse width
(2) INT4 to 7 interrupt, capture The INT4 to 7 input pulse width depends on the CPU operation clock and timer (9-bit prescaler). The following shows the pulse width for each clock. System Clock Prescaler Clock tINTBL (INT4 to 7 low-level pulse width) tINTBH (INT4 to 7 high-level pulse width) Unit Selected Selected Variable 20 MHz Variable 20 MHz Min Min Min Min
00 (fIFPH) 0 (fc) 1 (fs) (Note 2) 01 (fs) 10 (fc/16) 00 (fIFPH) 01 (fs) 8X 8XT 128X 8XT 100 0.1 0.1 0.1 500 244.3 6.5 244.3 8X 8XT 128X 8XT 100 0.1 0.1 0.1 500 244.3 6.5 244.3 s ns
Note 1: XT represents the frequency of the low-frequency clock fs. It is calculated at fs
32.768 kHz.
Note 2: When using fs as the system clock, fc/16 cannot be selected as the prescaler clock.
4.8
SCOUT Pin AC Characteristics
Parameter Variable
Symbol
10 MHz Max Min
40 30 40 30
20 MHz Min
15
Min
0.5X 10 20 10 20
Max
Max
Unit
High-level pulse width VCC High-level pulse width VCC Low-level pulse width VCC Low-level pulse width VCC
5V 3V 5V 3V
10% 10% 10% 10%
tSCH 0.5X 0.5X tSCL 0.5X
ns
15 ns
Measurement condition Output level: High 2.2 V/Low 0.8 V, CL
tSCH SCOUT tSCL
10pF
93CM40-19
2004-02-10
TMP93CM40
4.9
Timing Chart for Bus Request (BUSRQ )/Bus Acknowledge (BUSAK )
(Note 1)
CLK tBRC
BUSRQ
tBRC tCBAL tCBAH
BUSAK
tBAA AD0 to AD15, A0 to A23, CS0 to CS2 , R/ W , RAS CAS0 to CAS2 tABA (Note 2)
(Note 2)
RD , WR , HWR
ALE
Parameter
BUSRQ set-up time to CLK
Variable
Symbol
10 MHz Min
120
20 MHz Min
120
Min
120
Max
0.5x 0.5x 120 40
Max
270 90
Max
195 65
Unit
ns ns ns ns ns
tBRC tCBAL tCBAH tABA tBAA
CLK CLK
BUSAK
BUSAK falling edge BUSAK rising edge
Output buffer off to BUSAK to output buffer on
0 0
80 80
0 0
80 80
0 0
80 80
Note 1: Even if the BUSRQ signal goes low, the bus will not be released while the WAIT signal is low. The bus will only be released when BUSRQ goes low while WAIT is high. Note 2: This line shows only that the output buffer is in the off state. It does not indicate that the signal level is fixed. Just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capacitance. Therefore, to fix the signal level using an external resistor during bus release, careful design is necessary, as fixing of the level is delayed. The internal programmable pull-up/pull-down resistor is switched between the active and non-active states by the internal signal.
93CM40-20
2004-02-10
TMP93CM40
4.10 Recommended Oscillator
The TMP93CM40 is evaluated with various resonators. The evaluation results are displayed below to enable appropriate selection for any given application. Note: The load capacitance of the resonator consists of the load capacitors C1 and C2 which are to be connected, and the floating capacitance of the target board. Even if the specified values of C1 and C2 are used, there is a possibility that the oscillator will malfunction due to varying load capacitance on the target boards. Hence the oscillator's wiring patterns on the board should be designed to be as short as possible. It is recommended that evaluation of the resonators be conducted on the target board.
(1) Examples of resonator connection
X1 X2 XT1 XT2 Rd
Rd
C1
C2
C1
C2
Figure 1: Example of High-frequency Resonator Connection
Figure 2: Example of Low-frequency Resonator Connection
(2) Ceramic resonator: Murata Manufacturing. Co., Ltd. (Note 1)
Ta 20 to 80C
Parameter
Frequency (MHz)
Recommended Value
Recommended Resonator
C1 [pF]
CSA4.00MGU 30 (30) (Note 2) 30 (30) (Note 2) 5 5
C2 [pF]
30 (30) (Note 2) 30 (30) (Note 2) 5
Rd [k ]
VCC [V]
4.00 CST4.00MGWU High-frequency oscillation CSA10.00MTZ093 10.00 CST10.00MTW093 16.00 20.00 CSA16.00MXZ040 CSA20.00MXZ040
2.7 to 5.5 0
4.5 to 5.5 5
Note 1: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL: http://www.murata.com/ Note 2: For built-in condenser type
93CM40-21
2004-02-10
TMP93CM40
5.
Package Dimensions
P-QFP100-1414-0.50
Unit: mm
93CM40-22
2004-02-10

▲Up To Search▲

Price & Availability of TMP93CM40

	To Download TMP93CM40 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .